Recently, a Field-Programmable Gate Array (FPGA) has been noted as the hardware accelerators for high-performance computing. The distributed ring segmented bus (RSB) which connects an annular bus dynamically was proposed for the asynchronous bus between FPGA. In order to improve extensibility, the arbiters which control the divided buses connect the shortest path based on the wire delay. The distributed RSB system was designed as asynchronous circuits, and its operation was confirmed by implementing to four FPGA (Xilinx KC705). In addition, the effects of the FPGAs and wire delay on performance was clarified through the Monte Carlo simulation using implemented wire delay.
