Systematic reducing of metastable operations in CMOS D flip-flops

Yoichiro Sato
Yoshinobu Yamasoto
Masanori Saito
Hiroto Kagotani
Takuji Okamoto
Masahiro Kawai

This paper systematically examines a method of reducing metastable (MS) operation in an edge-trigger type CMOS D flip-flop (EDFF) and a master-slave type D flip-flop (MDFF). To obtain a general idea, the mechanism of the MS operation of each flip-flop (FF) contained in the EDFF and MDFF has been classified into three types by using the results of a computer simulation. The first type MS operation is completely suppressed by the `differential threshold method' (in which the threshold voltage of the FF is different from that of the following circuit element so that the propagation of the MS operation is suppressed). An additional feedback method (by which the duration of the MS operation is reduced) is applied to the rest of the types of operations. A new circuit for these methods is also suggested. The computer simulation shows that the increase rate of MS-operation duration against the input-phase difference (difference between the occurrence time of a clock pulse and the occurrence time of an input) is reduced to about 1/4, and that the range of the input-phase difference of MS operations is reduced to about 1/3, in both EDFF and MDFF.

Systems and Computers in Japan

31

3

20

28

10.1002/(SICI)1520-684X(200003)31:3<20::AID-SCJ3>3.0.CO;2-5

https://doi.org/10.1002/(SICI)1520-684X(200003)31:3<20::AID-SCJ3>3.0.CO;2-5