Minimum Verification Test Set for Combinational Circuits

Michinishi Hiroyuki
Yokohira Tokumi
Okamoto Takuji

A sufficient condition under which a minimum verification test set (MVTS) for a combinational circuit has 2w elements is derived, where w is the maximum number of inputs on which any output depends, and an algorithm to find an NVTS with 2w elements for any CUT with up to four outputs is described

Proc. First Asian Test Symposium (ATS ''92)

pp.14-19

14

19

10.1109/ATS.1992.224428

https://doi.org/10.1109/ATS.1992.224428
http://ci.nii.ac.jp/naid/120002305066
http://eprints.lib.okayama-u.ac.jp/30053